The present invention relates to a design technique of semiconductor devices, and particularly to a technique applied effectively to the design of semiconductor devices with the intention of enhancing the accuracy of delay calculation and crosstalk noise calculation and enhancing the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk.
According to the study on the design of semiconductor devices by the inventors of the present invention, it is necessary for the calculation of signal delay in an LSI device to evaluate the load capacitance of lines. Techniques pertaining to the calculation of line capacitance are described in Japanese Patent Unexamined Publications No. Hei 8(1996)-110915, No. Hei 6(1994)-120343, No. Hei 11(1999)-97539, No. Hei 11(1999)-259544, and No. Hei 5(1993)-342305, for example.
(1) The patent publication No. Hei 8(1996)-110915 discloses a technique of calculating the moduli of parallelism and moduli of crossing of all nets and evaluating a typical value of line capacitance based on the modulus of parallelism and modulus of crossing appearing frequently.
(2) The patent publication No. Hei 6(1994)-120343 discloses a technique of evaluating the line capacitance based on the pattern matching with numerous pattern models having their capacitance calculated in advance.
(3) The patent publication No. Hei 11(1999)-97539 discloses a technique of evaluating the degree of crosstalk (capacitance) based on the layout of parallel or cross lines of same or different layers.
(4) The patent publication No. Hei 11(1999)-259544 discloses a technique of calculating the capacitance factor based on the peripheral condition in terms of the distance to adjacent lines and cross lines.
(5) The patent publication No. Hei 5(1993)-342305 discloses a technique of calculating the capacitance between lines from parallel or overlapping line segments, thereby assessing the degree of crosstalk.
In regard to the above-mentioned techniques of calculating the line capacitance, the study by the inventors of the present invention has revealed the following affairs.
(1) The technique of the patent publication No. Hei 8(1996)-110915 is intended to evaluate the typical value of line capacitance from frequent moduli of parallelism and crossing of lines, instead of calculating the capacitance value based on the modulus of parallelism and modulus of crossing of each net or segment. It does not consider the variation of coupling capacitance with adjacent lines, besides the line-to-ground capacitance, depending on the modulus of crossing.
(2) The technique of the patent publication No. Hei 6(1994)-120343 is intended to evaluate the line capacitance based on pattern matching, instead of dealing with neighboring lines as parameters in terms of the modulus of parallelism and modulus of crossing. Accordingly, it compels to deal with a large amount of pattern data. Moreover, it can merely calculate the capacitance values of lines having their pattern data registered, and it does not consider the formulation of patterns into functions so as to facilitate the matching process.
(3) The technique of the patent publication No. Hei 11(1999)-97539 basically deals with the capacitance of parallel flat conductors in evaluating the degree of crosstalk, and it does not consider neighboring lines in different densities.
(4) The technique of the patent publication No. Hei 11(1999)-259544, which resembles the technique of No. Hei 6(1994)-120343 in evaluating the line capacitance based on pattern matching, does not deal with neighboring lines as parameter in terms of moduli of parallelism and crossing. Accordingly, it compels to deal with a large amount of pattern data. Moreover, it can merely calculate the capacitance of lines having their pattern data registered, and it does not consider the formulation of patterns into functions so as to facilitate the matching process.
(5) The technique of the patent publication No. Hei 5(1993)-342305, which resembles the technique of No. Hei 11(1999)-97539 in evaluating the degree of crosstalk by dealing with the capacitance of parallel flat conductors, does not consider neighboring lines in different densities.
Generally, the calculation of line capacitance for the purpose of calculating the signal propagation delay is based on the assumption of grounding of all lines except for the subject line. However, if the influence of crosstalk is taken into consideration, it is necessary to evaluate the coupling capacitance between the subject line and a noise-source parallel line and the line-to-ground capacitance with the assumption of grounding of all other lines.
The conventional techniques do not consider the coupling capacitance, or assume a constant coupling capacitance regardless of the density of neighboring lines, and therefore the accuracy of assessment of delay variation and checking of malfunctioning caused by crosstalk is not adequate. The increase of line-to-ground capacitance due to parallel lines is disregarded, even in the case of considering the coupling capacitance, and it is necessary for the evaluation of total capacitance, with parallel lines being removed, to make in advance a net list excluding the parallel lines and redo the calculation.
The calculation of total capacitance in consideration of the density of neighboring lines and the calculation of coupling capacitance are becoming particularly crucial in recent trends of microstructured wiring resulting from high-integration chips. Specifically, for minimizing the increase of line resistance, the line thickness cannot be made much smaller in exchange for the reduction of line width, which results in such a large aspect ratio (vertical-to-horizontal dimensional ratio) of line cross section of 1 or larger. Conventional flat lines have large proportions of the capacitance of parallel flat conductors, allowing the accurate evaluation of capacitance based on the multiplication of unit values of parallel and cross capacitance between layers and between lines evaluated in advance to overlapping areas and parallel distances of lines. Whereas, in regard to recent lines with large aspect ratios, the unit value of parallel capacitance varies depending on the density of neighboring cross lines, i.e., adjacent lines and cross lines have their capacitance values affecting each other.
On this account, the scheme of evaluating the capacitance of lines formed by automatic layout and wiring based on the search for the most-like pattern in a pattern library, as in the case of the above-mentioned prior art (e.g., No. Hei 6(1994)-120343) necessitates a huge amount of pattern data to be registered in the library by expending impractical time of several months.
The inventors of the present invention have found an effective scheme of enhancing the accuracy of calculation of the signal propagation delay caused by the line load, the accuracy of assessment of the delay variation caused by crosstalk, and the accuracy of checking of malfunctioning caused by crosstalk. The scheme is based on the registration of capacitance values in relation with parameters in terms of the modulus of parallelism and modulus of crossing unique to layouts of subject line (segment), instead of conducting the pattern matching mentioned above.
Accordingly, it is an object of the present invention to provide a design method of semiconductor device capable of accomplishing the enhancement of the accuracy of delay calculation and crosstalk noise calculation and the enhancement of the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk.
These and other objects and novel features of the present invention will be apparent from the following description and accompanying drawings.
Among the affairs of the present invention disclosed in this specification, representatives are briefed as follows.
The inventive design method adopts the scheme of evaluating the line-to-ground capacitance and coupling capacitance to be used for the delay calculation by basing the enhancement of evaluation accuracy on the neighboring line density. The inventive method defines the line-to-ground capacitance separately in terms of a base capacitance inherent to the existence of subject line, a cross capacitance increment caused by cross lines, and a parallel capacitance increment caused by adjacent lines. The inventive method evaluates the coupling capacitance in consideration of the modulus of crossing, evaluates the increment of line-to-ground capacitance caused by adjacent lines in consideration of the modulus of crossing, and separates the increment of line-to-ground capacitance value of adjacent lines, thereby evaluating the line-to-ground capacitance, with the parallel lines being removed, without the need of altering the net list.
More specifically, the inventive semiconductor device design method calculates the signal propagation delay by using the total capacitance (Ctotal) with the assumption of grounding of all lines except for the subject line in consideration of the actual load after the layout and wiring, checks the attainability of targeted in-cycle data transfer, repeats the layout and wiring until the targeted in-cycle data transfer becomes attainable, calculates the signal propagation delay by using the total capacitance (Ctotal) in consideration of the actual load after the layout and wiring, checks the attainability of targeted in-cycle transfer, repeats the modification of wiring until the targeted in-cycle transfer becomes attainable, calculates the level of crosstalk noise by using the total capacitance (Ctotal) and coupling capacitance (Cp) between the subject line and adjacent lines in consideration of the actual load after the layout and wiring, checks the occurrence of malfunctioning, repeats the modification of wiring until malfunctioning subsides, and uses the final data after the layout and wiring for mask data.
The inventive semiconductor device design method further evaluates the capacitance increment (xcex94Cp) of the total capacitance (Ctotal) for the cases with and without adjacent lines of the subject line, modifies the layout and line routing for a net having a negative slack even in the case without adjacent lines and no capacitance increment (xcex94Cp=0), and removes adjacent lines for a net having a negative slack of the case with adjacent lines and with a capacitance increment (xcex94Cp greater than 0), even though it has no negative slack in the case without adjacent lines and no capacitance increment (xcex94Cp=0).
The inventive semiconductor device design method registers in a table in advance total capacitance values of unit length in relation with parameters in terms of the modulus of parallelism and modulus of crossing, registers in tables in advance coupling capacitance values of unit length and capacitance increment values of unit length in relation with a parameter in terms of the modulus of crossing, calculates the actual modulus of parallelism and modulus of crossing from layout data after the layout and wiring, evaluates the total capacitance of unit length corresponding to the calculated modulus of parallelism and modulus of crossing and the coupling capacitance and capacitance increment of unit length corresponding to the modulus of crossing evaluated based on the interpolation or extrapolation process for table data, and multiplies the length of subject line to these unit values, thereby evaluating the total capacitance (Ctotal), coupling capacitance (Cp) and capacitance increment (xcex94Cp)